The present invention relates to a frequency synthesizer which is governed over time in accordance with sleep and awake cycles of a battery saving signal, and more particularly, to a control circuit coupled to the frequency synthesizer for enhancing the start-up operational behavior thereof with regard to the sleep and awake battery saving cycles.
A frequency synthesizer may be used in a radio receiver, for example, to generate a channel frequency signal which is used in a demodulator section to pass received information signals only within a desired channel represented by the generated channel frequency signal. Other applications of a frequency synthesizer include tone generating circuits for an electronic organ and oscillator circuits for controlling the operational frequency of a microprocessor, for example.
A frequency synthesizer generally includes a reference oscillator which generates a very stable reference frequency signal and another oscillator which is controlled by a voltage potential to generate the channel frequency signal. A feedback frequency signal is developed from the channel frequency signal via a divide by N circuit. A phase detector circuit operates to converge the phase of the feedback frequency signal to the phase of the reference frequency signal by adjusting the governing voltage potential of the voltage controlled oscillator. The elements of the phase detector, the voltage controlled oscillator, and the divide by N counter constitute, in combination, what is generally referred to as a phase locked loop.
In most phase locked loops, a storage device such as a capacitor, for example, is coupled between the phase detector and voltage controlled oscillator. The phase detector may govern the sourcing and sinking of current to and from the capacitor in order to adjust the voltage thereacross which governs the channel frequency of the signal generated by the voltage controlled oscillator. An example of such a phase locked loop is described in U.S. Pat. No. 4,167,711 issued to George Smoot on Sep. 11, 1979 and assigned to the same assignee as the instant application.
Certain electronic devices utilizing a frequency synthesizer, like radio receivers, for example, may be portable and powered by a battery. A battery saving circuit is generally included as part of such battery powered devices in order to conserve the usage of energy and prolong the life of the battery. An example of such a battery saving system for a radio receiver is described in U.S. Pat. No. 4,631,496 issued to Borras et al. on Dec. 23, 1986 and assigned to the same assignee as the instant application. Normally, the battery saving circuit generates a periodic signal having a duty cycle comprising sleep and awake cycles. During the sleep cycles, certain circuits of the radio receiver including the frequency synthesizer are rendered inoperative in order to conserve energy drain from the battery source. Correspondingly, during the awake cycles, such circuits are made operative to perform their respective operations.
The reference oscillator, the voltage controlled oscillator, and the phase detector circuits are generally governed by the battery saving signal. More specifically, the reference oscillator and voltage controlled oscillator are inhibited from generating their respective frequency signals during the sleep cycles and restarted at the commencement of each awake cycle. In addition, the charging circuit, which is governed by the phase detector to adjust the voltage across the storage capacitor, is rendered in a floating condition during the sleep cycles such that such capacitive stored voltage may be maintained throughout the sleep cycle to enhance the start up time of the phase locked loop at the commencement of each awake cycle.
It is recognized that the reference oscillator and voltage controlled oscillator both require a start up time interval after enablement by the battery saving signal in order to settle and stabilize and generate an effective frequency signal. It is further recognized that when the frequency synthesizer is used in a receiver for demodulation, the information developed by the demodulation circuitry of the receiver is unreliable throughout this start up time interval. Accordingly, in order to compensate for these undesirable start up conditions, the sleep cycles are generally made shorter in the periodic battery saving signal.
The technique of floating the charging circuit and maintaining the voltage across the storage element throughout the sleep interval ensures that the voltage controlled oscillator will generate a signal at a desired frequency at each start up. However, this technique is corrupted by the observation that it is highly unlikely that the reference oscillator and voltage controlled oscillator will produce effective frequency signals concurrently upon being awakened. Since these frequency signals govern the operation of the phase locked loop, if one frequency signal is rendered effective before the other after both oscillators have been awakened, the phase detector will respond solely to the effective frequency signal to alter the maintained voltage of the storage device substantially away from that which was presumed to be a desirable start up value. If left uncompensated, this perturbation in oscillator controlled voltage may cause a longer start up time for the oscillators and the phase locked loop which would lead to shorter sleep cycles and, ultimately, shorter battery life.
Thus, it is believed of paramount importance to ensure that the desired start up voltage for the voltage controlled oscillator is maintained from the commencement of each awake cycle throughout the start up settling and stabilization periods of the oscillator circuits to guarantee a faster phase locked condition for the frequency synthesizer to produce the desired channel frequency. In so doing, an effective channel frequency signal is produced in a shorter period of time, thus allowing for longer sleep cycles which should prolong the life of the battery source.